The success of any semiconductor industry crucially depends upon the number of correct chips it produces (yield) within a given time window. Yield analysis has thus become a major issue for the progress of any electronic industry. For current nanometer-scale technologies, yield remains very low during the initial stages of manufacturing. This is mainly because the manufacturing and lithographic techniques still remain at 193 nm whereas the technology nodes have been driven below 60 nm. The process-design interactions lead to design rule violations that further result in a class of faults that are termed Systematic Defects, i.e., a class of faults which occur because of various design rule violations which are caused by process-design interactions. Such process-design interactions mainly occur because of the limitations of the manufacturing techniques in the current nanometer era.
With technology nodes now being driven much below 65 nm, timing characterization has become an extremely challenging task for the Electronic Design Automation (EDA) industries. Techniques like non-linear delay modeling (NLDMs) have been conventionally used for modeling the delay of the digital gates.
For a given technology model and for a given process corner, the conventional NLDM characterization characterizes the delay of the gate in a look up table which stores the delay of the gate for a particular input voltage slew and output load capacitance. The delay of the gate corresponding to different input slews (rising/falling) are computed with different output loading capacitances (Ceff) using SPICE and stored in a 2 dimensional lookup table. See, for example, a reference to J. Qian, S. Pullela, and L. Pillage entitled “Modeling the effective capacitance for the RC interconnect of CMOS gates,” IEEE Trans. on CAD, vol. 13, no. 12, pp. 1526-1535, December 1994. During the timing analysis, whenever a particular gate is encountered, first a Ceff is computed from the corresponding output loading. Both the Ceff value and the input slew at the gate are used to look up the delay value from NLDM look-up table using non-linear approximations.
The need for accurate modeling of cell has become acute at advanced technology nodes. Several effects such as Multiple Input Switching, Nonlinear Pin Capacitance, etc., which were considered as second order terms at earlier technology nodes are showing major impact at advanced technology nodes. Owing to the highly resistive interconnect and noisy waveforms, table lookup techniques like NDLM that have been conventionally used to predict the gate delay for a given input slew and output loading capacitance (Ceff) are no longer able to estimate accurate delays thereby resulting in high errors during the timing analysis of digital designs.
The emergence of Current Source models such as described in a reference to P. Li and E. Acar entitled “Waveform independent gate models for accurate timing analysis”, Proc ICCD, pp. 363-365, October 2005, provides an efficient solution to this problem by modeling the digital cells as a voltage controlled DC-current source along with either various nonlinear parasitic capacitances or voltage controlled charge sources (VCCS) embedded in to the model.
The characterization of VCCS is highly important for accurately modeling of the nonlinear cell behavior. However, very little attention has been paid towards characterization of VCCS in the literature. In known techniques such as described in a reference to C. Amin, C. Kashyap, N. Menezes, K. Killpack and E. Chiprout entitled “A multi-port current source model for multiple-input switching effects in CMOS library cells,” Proc. of DAC, pp. 247-252, July 2006, the output and input ports of the cell are either forced to a constant voltage or fast ramp voltages (i.e., quickly rising/falling linear voltage waveforms) are applied at them.
For instance, existing current source models (BLADE and RAZOR) proposed in the reference to J. F. Croix and D. F. Wong entitled “Blade and Razor: Cell an interconnect delay analysis using current-based models,” Proc. of DAC 2003, pp. 386-389, model any digital CMOS gate as a voltage controlled current source with a linear output capacitance. The voltage controlled current source captures the DC characteristics of the gate whereas the linear output capacitance captures the dynamic behavior of the gate for different slews. The model proposed in the J. F. Croix et al. reference itself is in a very nascent form and the modeling itself is very inaccurate as it assumes a linear output capacitance at the output of the cell. Also, this linear capacitance is characterized using SPICE by providing ramps at the input of the cell and measuring the output current. This characterization method is quite inaccurate.
FIG. 1 depicts the BLADE current model 10 for modeling delay of CMOS digital cells. These models characterize a DC voltage controlled current source 12 along with the linear output capacitance using SPICE characterized on a “[Vi×Vo] space” which denotes a set of all the possible voltage input and voltage output [Vi Vo] combinations. In this model, input capacitances are neglected, output capacitance 15 is linear and the non-linear nature of capacitances is neglected. The characterization for such current-source models is actually independent of the output loading and hence no Ceff modeling is required in such a scenario. Hence, such kind of modeling actually assists in obtaining load independent device characterization. That is, the model parameters which are characterized are independent of output loading and depend only upon the voltage at input and output pins of the cell rather than the ‘characterization procedure’ itself which does depend upon the output capacitances which are chosen for the characterization purpose and helps generate an output waveform for a given arbitrary waveform (nonlinear/noisy) at the gate input for a given output loading (resistive/capacitive). Since the complete output waveform is generated for a given input waveform, the inaccuracy in NLDM due to the interpolation and due to handling of noisy/nonlinear waveforms is completely eliminated from such a model.
FIG. 2 depicts a more generic model for CSMs by modeling non-linear capacitance at the driving gate's output using a voltage controlled charge source (VCCS) such as described in the above-identified reference to P. Li and E. Acar. As shown in FIG. 2 this model consists of a two stage waveform independent gate model 20 (WiM) that introduces a 2nd order linear RC stage 22 at the input which provides robustness for modeling complex multi stage gates. In the current source model 20 shown in FIG. 2, the VCCS is characterized by holding the output at constant voltage threshold and providing a ramp at the input.
FIG. 3 depicts a multiport CSM model for delay and noise characterization such as described in above-mentioned reference to C. Amin, C. Kashyap, et al. As shown in FIG. 3, the multiport CSM model 30 targets the problem of multiple input switching (MIS) by modeling various input/output and miller capacitances at any input/output node in the form of voltage controlled charge source (VCCS). The non-linear DC current source at each port captures the DC behavior of the cell and various nonlinear voltage controlled charge source at each port represent the dynamic behavior of the cell output. The VCCS of charge value ‘Qi’ at each port ‘Pi’, i=1, . . . , n2, n−1, n, depends on the instantaneous value of voltage ‘Vi’ at each port ‘i’ as follows:Qi=F(V1,V2, . . . , Vn)
Likewise, in view of FIG. 3, at any port Pi,IR,pi=Gi(V1,V2, . . . , Vn)Qc,pi=Fi(V1,V2, . . . , Vn)and the instantaneous value of current at any port ‘k’ is:Σi=1n((∂Qc,pk/∂Vt)×(∂Vt/∂t))ipk=iR,pk+Σi=1n((∂Qc,pk/∂Vi)×(∂Vi/∂t))
The modeling of charge at each port in such a way helps capture the effects of both—the nonlinear output capacitance and the nonlinear miller capacitances linked at each port. The charge source Qc,pi (at each port P1, . . . Pn) is characterized by forcing a quick ramp at each port i and dynamically measuring the corresponding current entering at each port at specific time steps. In this technique, there are provided quick ramps at all the ports—whether input or output—and hence they have forced the output with a quick ramp waveform. Thus, for example, to characterize the charges at each port corresponding to a voltage combination of (V1, V2, . . . , Vn) at ports (1,2, . . . , n), a quick ramp from ‘0’ to a voltage value ‘V1’ is applied at port 1, a quick ramp from ‘0’ to a voltage value ‘V2’ is applied at port 2 and so on and the currents entering each port are measured at specific instants of time. The integral of the current entering the charge source (at each port) over a large period of time provides the value of charge Q(V1, V2, . . . , Vn).
The main drawback of this technique is that it doesn't include the modeling of internal nodes of the cell in to account. For complex multistage cells, the charges and currents at different ports of the cell not only depend upon the voltages at different ports, but also on the voltages of internal nodes.
Also, this technique lacks accuracy from the point of view of characterizing the charge sources at each port. Firstly, to characterize the charges at each port at voltage combinations (V1, V2, . . . Vn), the voltage at each port ‘i’ is forced to go from ‘0’ to a value ‘Vi’ which is not a natural behavior of the cell; in real circuits, outputs are never forced to take any values.
It would be highly desirable to provide a novel technique to characterize VCCS representing dynamic behavior of a cell in the modeling of digital cells.
Moreover, it would be highly desirable to provide a method and system for more accurately modeling semiconductor device performance and provide an integrated approach for various cell analyses like timing, cell delay, noise, and power where a VCCS is used to represent the dynamic behavior of the digital cell.